Programmable logic devices (PLDS) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Conventionally, such a bitstream is generated using a hardware description language (“HDL”), such as Verilog or Very High Speed Integrated Circuit (“VHSIC”) HDL (“VHDL”), to provide a textual description of circuitry (“text-circuit description”) which is synthesized and implemented. Accordingly, a design described through an HDL is a functional description, which is converted into a text-circuit description using one or more synthesizer tools or programs. Mapping, placement, and routing of components/signals then implement this synthesis from which comes the bitstream. Due to the large number of components and interconnections, mapping, placing and routing can consume a significant amount of computer time (“runtime”). A more recent addition to HDL involves use of a programming language, such C/C++ as in SystemC from Synopsys of Mountain View, Calif., to provide a circuit synthesis.
Circuit synthesis is used in designing all types of complex integrated circuits. One use is for designing hardwired circuitry, such as in FPGAs, processors, Application Specific Standard Products (ASSPs), and the like. Another use is for designing Application Specific Integrated Circuits (ASICs), including ASIC standard cells, where a vendor or customer uses synthesis tools to programmatically configure logic built on such an integrated circuit. Another use of synthesis tools is programmatically configuring a portion of an FPGA to provide a design. For purposes of clarity, an FPGA integrated circuit is described, though it will be apparent that any integrated circuit of sufficient complexity designable with synthesis tools may be implemented.
Once a design is created and implemented for an FPGA, it may be improved for performance, debugged, or the like. The process for creating a design for an FPGA, or other circuit, can involve iterative use of synthesizing and implementing. This iterative process is sometimes referred to as “incremental design,” and is described in additional detail in U.S. Pat. No. 5,867,396. Whether an FPGA design is being altered after meeting all timing requirements to improve performance, or is being changed to improve performance to meet all timing requirements, or other goal(s), rerunning a mapper (“MAP program”), and a placer and router (“PAR program”) after each design change is time consuming. Thus, runtimes for mapping, placing and routing for implementation may significantly impact design cycle time, especially if multiple debugging iterations are done.
In incremental design of the past, if there were some percentage of change in instances of circuitry as coded, whether Verilog modules or VHDL entities for example, all unchanged circuitry would be left without any further mapping, placing and routing (“locked down”). The changed circuitry could then be re-mapped, re-placed and re-routed subject to avoidance of locked down circuitry. Classically, there was no differentiation with respect to hierarchy of logic, this was a flat instance “name-based” guide for incremental design. By “name-based,” it is meant a matching or comparison of specific names used.
In U.S. Pat. No. 5,867,396, it was recognized that sometimes using name changes in a synthesis output (“netlist”) as an indicator as to circuit changes in a design could be misleading. Thus, in instances of logic a name may be changed without actually having a corresponding change in circuitry from a prior naming. Accordingly, a check was made to determine whether a change in name actually amounted to a change in circuitry to potentially reduce the amount of circuitry to be re-mapped, re-placed and re-routed.
However, each of the above-described types of incremental design tends to be disfavored owing to inability to meet performance goals. Thus, conventional incremental design re-maps, re-places and re-routes an entire design in order to meet integrated circuit performance goals at the expense of runtime. Thus, multiple debugging iterations can significantly impact design cycle time. Furthermore, as integrated circuits become more complex by having more circuits, runtimes may increase.
Today, there is hierarchical synthesis. Hierarchical synthesis allows for multiple groupings of blocks of logic. Examples of hierarchical design methodologies, include:                Having all critical paths within a grouping of instantiated logic.        Having inputs or outputs (I/Os) registered at boundaries of a grouping of instantiated logic.        Having a top hierarchical level (“top level”) having only instantiated modules or entities, IOB logic and clock logic.        
Accordingly, it would be both desirable and useful to provide means to reduced runtime for incremental design while doing a better job of facilitating meeting performance goals.